Patrick Satarzadeh

Patrick SatarzadehPatrick SatarzadehPatrick Satarzadeh

About

Patrick Satarzadeh is a highly experienced systems engineer with a strong background in digital signal processing algorithm development as well as expertise in analog/photonic circuit modeling and calibration. He has held senior positions at leading technology companies such as Lumentum, Tektronix, Xilinx and Texas Instruments where he has made significant contributions to the development of cutting-edge technologies.

Previously, Patrick co-founded Areanna AI, a company that pioneered the development of in-memory compute engines for next-generation AI accelerators. The company's successful chip tapeout led to an early acquisition, validating its innovative approach and market potential

Throughout his career, Patrick has demonstrated a strong ability to design and implement complex digital and analog algorithms, particularly in the areas of ADCs, DACs, and SerDes. He is also proficient in numerical modeling and development of signal processing and communication systems using MATLAB/Simulink/Python.

Patrick's technical skills extend to circuit design in Spice and Cadence, as well as AI algorithm development using open-source frameworks like TensorFlow and TensorFlow Lite. A member of IEEE/Optica and a frequent reviewer for conference and journal papers, Patrick actively contributes to the advancement of his field. He closely follows industry developments in PCIe, UCIe, Ethernet, and OIF

Selected Publications

Digital Correction of Time Interleaved DAC Mismatches

A 20mW 61dB SNDR (60MHz BW) 1b 3rd-order continuous-time delta-sigma modulator clocked at 6GHz in 45

Time-interleaved DACs (TIDACs) are fast but suffer from mismatch distortion. This work proposes a digital filter-based pre-processing technique with a calibration algorithm to calculate optimal filter coefficients, significantly reducing mismatch distortion with minimal complexity.

A 20mW 61dB SNDR (60MHz BW) 1b 3rd-order continuous-time delta-sigma modulator clocked at 6GHz in 45

Continuous-Time ΔΣ Modulators are widely used in ADCs, but high sampling rates require minimizing Excess Loop Delay (ELD). ELD includes comparator, DAC, and parasitic delays. For high-speed modulators, ELD impacts stability. This paper presents techniques to minimize ELD and ensure stability, enabling a 6GHz 3rd-order modulator in 45nm CMOS.

Equalizer Design and Performance Trade-Offs in ADC-Based Serial Links

A 20mW 61dB SNDR (60MHz BW) 1b 3rd-order continuous-time delta-sigma modulator clocked at 6GHz in 45

A 5 Gb/s Link With Matched Source Synchronous and Common-Mode Clocking Techniques

This paper explores using non-uniform ADCs in high-speed serial receivers with decision-feedback equalization (DFE) to improve performance. It shows how to optimize ADC thresholds for minimum bit-error rate (BER) and proposes a simplified receiver architecture called RS-PRDFE that eliminates unnecessary components. Results from a 10 Gb/s ADC-based receiver in 65 nm CMOS demonstrate that RS-PRDFE achieves the BER of a 3-4-bit uniform ADC using only 4 data slicers. Adding analog linear equalizers can further reduce the number of slicers needed.

A 5 Gb/s Link With Matched Source Synchronous and Common-Mode Clocking Techniques

A parametric polyphase domain approach to blind calibration of timing mismatches for M-channel time-

A 5 Gb/s Link With Matched Source Synchronous and Common-Mode Clocking Techniques

This work presents a 5 Gb/s source-synchronous signaling system with a new clock/data skew minimization technique for improved jitter tolerance and fast turn-on. It also explores embedding the clock in the common-mode signal to reduce delays. A 40 nm CMOS test chip shows significant margin improvements under realistic noise conditions. The embedded clocking approach achieves comparable performance, offering a solution for pin-constrained designs.

A parametric polyphase domain approach to blind calibration of timing mismatches for M-channel time-

This paper proposes a low-complexity blind calibration algorithm to correct timing mismatches in time-interleaved ADCs. It uses a polyphase domain model to derive efficient correction and estimation methods that work together, requiring minimal oversampling and enabling adaptation to drifting mismatches.

Digital Calibration of a Nonlinear S/H

A parametric polyphase domain approach to blind calibration of timing mismatches for M-channel time-

This paper presents a mixed-signal model and digital correction for nonlinearity in sample and hold (S/H) circuits. The model, based on Volterra series, shows that S/H circuits expand signal bandwidth. A digital correction using Volterra series inverses, combined with adaptive parameter estimation, significantly improves spurious free dynamic range (SFDR) for oversampled signals with low computational cost.

Adaptive Semi-blind Calibration of Bandwidth Mismatch for Two-Channel Time-Interleaved ADCs

This paper proposes a digital method to fix bandwidth mismatch errors in time-interleaved ADCs. It uses a hybrid filter-bank model to estimate and correct these errors. A small test tone helps estimate the mismatch without disrupting normal ADC operation. The correction uses simple digital filters to remove the main error effects. Simulations show this method effectively reduces unwanted distortions.

Digital calibration Methods for Sample-and-Hold Circuits

Adaptive Semi-blind Calibration of Bandwidth Mismatch for Two-Channel Time-Interleaved ADCs

This thesis focuses on calibrating sample-and-holds (S/Hs). It explores two main calibration approaches:

Correcting mismatches between S/Hs in time-interleaved ADCs.
Removing distortion caused by a single S/H's inherent nonlinearity.

Both approaches involve separate estimation and correction networks. The estimation network uses adaptive signal processing to continuously track and estimate analog imperfections. The correction network then uses these estimates to adjust the S/H operation and improve performance. These networks can operate independently (disjoint) or work together in tandem (connected).

Physical and Filter Pinna Models Based on Anthropometry

Adaptive Semi-blind Calibration of Bandwidth Mismatch for Two-Channel Time-Interleaved ADCs

Physical and Filter Pinna Models Based on Anthropometry

This paper explores how ear shape (pinna anthropometry) affects sound localization cues. By analyzing and modeling how isolated pinnae affect sounds from the front (PRTFs), it shows that a simple filter model with parameters based on ear shape can accurately represent these cues. While it's sometimes possible to estimate these parameters from a few ear measurements, directly predicting them from ear shape remains an unsolved challenge.

Featured Patents

Integrated Communication Link Testing

Digital signal processing waveform synthesis for fixed sample rate signal sources

Real-time jitter impairment insertion for signal sources

This test device analyzes analog signals from a DUT (Device Under Test). It uses an ADC (Analog to Digital Converter) to digitize the signal, which is then analyzed by a receiver in one FPGA (Field Programmable Gate Array). A transmitter in a second FPGA generates a digital output signal, converted back to analog by a DAC (Digital to Analog Converter) and sent back to the DUT. The receiver and transmitter share data about the testing environment over a high-speed link.

Real-time jitter impairment insertion for signal sources

Digital signal processing waveform synthesis for fixed sample rate signal sources

Real-time jitter impairment insertion for signal sources

A test and measurement device having a signal source, including an impairment generator configured to output an impairment and a waveform synthesizer. The waveform synthesizer receives an input digital signal to be synthesized, receives the impairment, and synthesizes a synthesized digital signal based on the input digital signal and the impairment. The test and measurement instrument also includes a fixed sample rate digital-to-analog converter configured to receive a clock signal and the synthesized digital signal and output an analog signal.

Digital signal processing waveform synthesis for fixed sample rate signal sources

A test and measurement instrument including a digital-to-analog converter having an output sample rate configured to receive a digital sample waveform and a reference clock and output an analog waveform at the sample rate, a waveform synthesizer configured to receive an input waveform having a baud rate and output a digital sample waveform having a baud rate less than the sample rate of the digital-to-analog converter, and a port configured to output the analog waveform.

Noise reduction in digitizing systems

Circuits for and methods of receiving data in an integrated circuit

Noise reduction in digitizing systems

Disclosed are systems and methods related to a noise reduction device employing an analog filter and a corresponding inverse digital filter. The combination and placement of the filters within the systems aids in reducing noise introduced by processing the signal. In some embodiments, the combination of filters may also provide for increased flexibility when de-embedding device under test (DUT) link attenuation at higher frequencies. Further, the filters are adjustable, via a controller, to obtain an increased signal to noise ratio (SNR) relative to a signal channel lacking the combination of filters. Additional embodiments may be disclosed and/or claimed herein.

Signal loss detector

Circuits for and methods of receiving data in an integrated circuit

Noise reduction in digitizing systems

In an example, an apparatus for detecting signal loss on a serial communication channel coupled to a receiver includes an input, a detector, and an output circuit. The input is configured to receive decisions generated by sampling the serial communication channel using multiplexed decision paths in a decision feedback equalizer (DFE). The detector is coupled to the input and configured to monitor the decisions for at least one pattern generated by the multiplexed decision paths in response to absence of a serial data signal on the serial communication channel. The output circuit is coupled to the detector and configured to assert loss-of-signal in response detection of the at least one pattern by the detector.

Circuits for and methods of receiving data in an integrated circuit

A circuit for receiving data in an integrated circuit is described. The circuit comprises a receiver configured to receive an input signal and to generate output data based upon the input signal, the receiver having a level detection circuit coupled to receive the input signal; and a calibration circuit coupled to the receiver, the calibration circuit having an input for receiving the input signal; an error detection circuit coupled to the input, the error detection circuit coupled to receive the input signal, a first reference voltage and a second reference voltage; and a control circuit coupled to an output of the error detection circuit, wherein the control circuit selectively generates either an offset control signal or an amplitude control signal based upon comparisons of the input signal to the first reference voltage and the second reference voltage. A method of receiving data is also disclosed.

Channel adaptive receiver switchable from a digital-based receiver mode to an analog-based receiver

In a method for channel adaptation, an analog input signal is received with a bimodal receiver via a communications channel. The analog input signal is converted to a digital input signal with an analog-to-digital converter of a digital receiver of the bimodal receiver. Channel coefficients are detected for the digital input signal associated with the communications channel. The channel coefficients indicate a number of post-cursor taps of the bimodal receiver to be used to provide an equalized digital output signal from the digital input signal. It is determined whether the number of post-cursor taps or a value associated therewith is equal to or less than a threshold number. A switch from the receiving of the analog input signal by the digital receiver to an analog receiver of the bimodal receiver is made to provide the equalized digital output signal for the analog input signal.

Excess loop delay compensation for a continuous time sigma delta modulator

Channel adaptive receiver switchable from a digital-based receiver mode to an analog-based receiver

A method and corresponding apparatus are provided. In operation, an analog signal is integrated with an integrator to generate an integrated analog signal. The integrated analog signal is compared, in synchronization with a first clock signal and a second clock signal, to a reference voltage with a plurality of comparators to generate a comparator output signal. A feedback current is then generated, in synchronization with the second clock signal, from the comparator output signal. The feedback current is fed back to at least one of the comparators, and the comparator output signal is latched in synchronization with the first clock signal to generate a latched output signal. This latched output signal is converted to a feedback analog signal, and a difference between the analog signal and the feedback analog signal is determined.

Method and apparatus for performing data conversion with non-uniform quantization

Channel adaptive receiver switchable from a digital-based receiver mode to an analog-based receiver

Method and apparatus for performing data conversion with non-uniform quantization

A method for converting a sampled analog signal into digital is provided. An input signal is sampled at a sampling instant to generate a sample voltage. A first current is then applied to a node to change a voltage on the node, and a first interval to change the voltage on the node to a reference voltage from the sample voltage using the first current is determined. A second current is then applied to the node to change a voltage on the node prior to a subsequent sampling instant, and a determination of a second interval to change the voltage on the node to the reference voltage from the sample voltage using the second current is made.

Pipelined ADC inter-stage error calibration

Method for calibrating a pipelined continuous-time sigma delta modulator

Compressive sensing analog-to-digital converters

An analog-to-digital converter (ADC) is provided. The ADC includes a plurality of pipelined ADCs and an adjustment circuit. Each pipelined ADC is adapted to receive an analog input signal, has an adjustable transfer function, and includes a compensator. The adjustment circuit is coupled to each pipelined ADC to be able to adjust the transfer function for each pipelined ADC so as to generally eliminate an estimation ambiguity. Additionally, the adjustment circuit estimates an inter-stage error that includes at least one of an inter-stage gain error and a DAC gain error and adjusts the compensator for each pipelined ADC to compensate for the inter-stage error.

Compressive sensing analog-to-digital converters

Method for calibrating a pipelined continuous-time sigma delta modulator

Compressive sensing analog-to-digital converters

Compressive sensing is an emerging field that attempts to prevent the losses associated with data compression and improve efficiency overall, and compressive sensing looks to perform the compression before or during capture, before energy is wasted. Here, several analog-to-digital converter (ADC) architectures are provided to perform compressive sensing. Each of these new architectures selects resolutions for each sample substantially at random and adjusts the sampling rate as a function of these selected resolutions.

Method for calibrating a pipelined continuous-time sigma delta modulator

Traditionally, pipelined continuous-time (CT) sigma-delta modulators (SDM) have been difficult to build due at least in part to the difficulties in calibrating the pipeline. Here, however, a pipelined CT SDM is provided that has an architecture that is conducing to being calibrated. Namely, the system includes a digital filter and other features that can be adjusted to account for input imbalance errors and well as quantization leakage noise.

PatrickSatarzadeh